Quantum Computing Modalities: Principles, Recent Progress and Industry Landscape
Yulin Liu
Quantum Economics AI Lab
Superconducting · Trapped ion · Neutral atom · Photonic · Silicon spin · Colour centres · Majorana topological (as of September 2026)
Key takeaways
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1 Why the “modality race” is not over
A classical bit is either 0 or 1; a quantum bit (qubit) can be in a superposition of 0 and 1, and several qubits can be entangled. For specific problems, such as factoring large numbers or simulating chemistry and materials, quantum algorithms exploit interference and entanglement to achieve speed-ups that classical algorithms cannot match. But a “qubit” is an abstract mathematical object; it must be carried by a real physical system: superconducting circuits, trapped ions or atoms, photons, electron spins in semiconductors, crystal defects, or the still-unconfirmed Majorana quasiparticles.
In 2000 DiVincenzo summarised five basic requirements for a physical quantum computer: scalable, well-characterised qubits; the ability to initialise them; coherence times much longer than gate times; a universal gate set; and qubit-specific measurement[1]. More than two decades later, the modalities still score differently on these criteria: some have long coherence but slow gates, some are fast but need temperatures near absolute zero, some are easy to mass-produce but suffer from poor uniformity. Because no physical system dominates on every dimension, the industry still pursues many modalities in parallel (Figure 1).
The categories used in this report follow common industry practice, grouping systems by their main physical carrier or encoding architecture; they are not strictly mutually exclusive. For example, transmon, fluxonium and bosonic cat qubits all sit within the superconducting family (cat qubits are also a bosonic encoding approach), Majorana qubits combine a materials platform with a topological encoding paradigm, and Photonic Inc.'s approach is based on optically linked silicon spin qubits.

Figure 1 Main physical carriers of qubits and their typical trade-offs (schematic). Temperatures and gate times are order-of-magnitude indications and vary by device.
Five core metrics capture most of the differences between modalities: fidelity (the probability that an operation goes wrong; two-qubit gates are usually the bottleneck), coherence time (how long quantum information survives), gate speed (how many operations can be performed per unit time), connectivity (whether any two qubits can interact directly), and scalability/manufacturability (whether a million qubits can be built at acceptable cost). Preskill's “noisy intermediate-scale quantum” (NISQ) concept[2] describes exactly this stage: tens to hundreds of qubits, but noise limits the depth of circuits that can be run reliably. Large-scale, general-purpose and reliable quantum computing is widely regarded as requiring quantum error correction.
2 Quantum error correction: the common destination
The basic idea of quantum error correction (QEC) is to encode the information of one “logical qubit” redundantly in an entangled state of many physical qubits, and to detect and correct errors by repeatedly measuring “stabilisers” without reading out (and thus destroying) the protected information[3]. The threshold theorem states that if the physical error rate is below a certain threshold, increasing the size of the code (the code distance d) suppresses the logical error rate exponentially. For common noise models and standard surface-code circuits this threshold is typically of order 1%, with the exact value depending on the noise model, decoder and gate set[4]. A common metric in recent surface-code experiments is the error-suppression factor Λ, the factor by which the logical error rate falls each time the code distance increases by 2. Under a given code, decoder and noise conditions, Λ > 1 indicates that the logical error rate decreases with distance, i.e. below-threshold error suppression has been observed.
2023–2026 marked the transition of QEC from proof of principle to engineering (Figure 2):
- Superconducting: In 2023 Google observed for the first time that a d=5 surface code outperformed d=3[5]; in 2024 it ran a d=7 surface code on 101 qubits of its Willow chip with Λ = 2.14 ± 0.02, a logical error rate of 0.143% per cycle, and a logical-qubit lifetime 2.4 times that of its best physical qubit[6]. At the end of 2025, USTC's Zuchongzhi 3.2 reached Λ = 1.40 on a d=7 surface code using all-microwave leakage suppression[7].
- Neutral atoms: In 2023 a Harvard/MIT/QuEra team ran algorithms with up to 48 logical qubits on 280 atoms[8]. In 2025 the team used up to 448 atoms to demonstrate key elements of a fault-tolerant architecture: below-threshold surface-code operation (a factor of 2.14), transversal gates and lattice surgery, universal logic based on 3D codes, and deep circuits with up to 96 high-rate [[16,6,4]] logical qubits[9]. The surface-code below-threshold result used no postselection, whereas some deep-circuit results relied on substantial postselection and are therefore not directly comparable with logical qubits run deterministically. The same group proposed “algorithmic fault tolerance”, which reduces runtime overhead by roughly a factor of d[10], and demonstrated magic-state distillation at the logical level[11].
- Trapped ions: On the 98-qubit Helios system, Quantinuum realised 48 error-corrected logical qubits and 94 error-detected logical qubits that outperformed unencoded physical qubits[12]; joint work by Microsoft and Quantinuum combined error correction and detection to further reduce logical error rates[13].
- More efficient codes: IBM's bivariate bicycle code (the “gross code”, [[144,12,12]]) needs roughly one-tenth as many physical qubits as the surface code for comparable protection, but requires non-nearest-neighbour connectivity[14]; AWS concatenates bosonic “cat” qubits with a repetition code, using the hardware itself to suppress one class of errors[15].

Figure 2 Representative logical-qubit milestones (2023–2026). The vertical axis shows the number of logical qubits operated simultaneously in a single experiment. Filled markers denote error correction; hollow markers denote error detection or results relying on substantial postselection. Code distance, postselection and correction-versus-detection differ greatly between experiments, so the points should not be compared directly. Sources: [5–9,12,16].
It is worth stressing that the “number of logical qubits” is not in itself a good cross-platform metric. A distance-2 error-detecting code and a distance-7 error-correcting code can both be called “logical qubits”, yet the latter offers protection that is orders of magnitude stronger. More meaningful metrics are the error rate per logical operation, the number of consecutive rounds of error correction, whether results depend on postselection (discarding part of the experimental runs), and the physical-to-logical qubit overhead. All logical-qubit numbers in this report should be read in that context.
3 The seven modalities in detail
3.1 Superconducting qubits: fastest gates, earliest industrialisation
Principle. Superconducting qubits are microwave circuits fabricated on chips from superconductors such as aluminium or niobium. Their key element is the Josephson junction, a non-linear “inductor” that makes the circuit's energy levels unequally spaced, so that the lowest two levels can be used as 0 and 1. The mainstream transmon design greatly improves coherence by reducing sensitivity to charge noise[17]. Chips operate at about 10 mK in dilution refrigerators and are controlled with microwave pulses; two-qubit gates typically take only tens of nanoseconds.
Recent progress. Google first claimed “quantum supremacy” with the 53-qubit Sycamore processor in 2019[18]. In 2025, its “Quantum Echoes” experiment on Willow, which measures a second-order out-of-time-order correlator (OTOC(2)), provided a verifiable beyond-classical computation: for this specific benchmark, the authors estimate that the best known classical simulation on the Frontier supercomputer would take about 13,000 times as long as the quantum data collection[19]. USTC's 105-qubit Zuchongzhi 3.0 achieves 99.62% two-qubit gate fidelity and, in random-circuit sampling with 83 qubits and 32 cycles, pushes the classical simulation cost about six orders of magnitude above that of Google's 2024 experiment[20]. In November 2025 IBM delivered the 120-qubit Nighthawk processor and the Loon test chip validating long-range couplers; on its roadmap, Kookaburra (2026) is to be the first module storing information in qLDPC codes with a logical processing unit, and Starling (2029) targets 200 logical qubits and 100 million logical gates[21]. Notably, in March 2026 Google announced that it would add a neutral-atom programme alongside superconducting qubits, arguing that superconducting qubits are “easier to scale in time” (circuit depth) and neutral atoms “easier to scale in space” (qubit count); Google still expects commercially relevant superconducting quantum computers by the end of the decade[22]. Even the industry leaders are hedging their modality risk.
Bottlenecks. A single transmon and its readout resonator occupy millimetre-scale area, so a million qubits require modular multi-chip interconnects; each qubit needs several microwave lines, making cryostat wiring and heat load hard constraints; and two-level-system (TLS) defects at material interfaces cause qubit parameters to drift over time, requiring frequent recalibration.
3.2 Trapped ions: the fidelity benchmark
Principle. Charged atoms (such as ¹⁷¹Yb⁺ or ¹³⁷Ba⁺) are levitated by radio-frequency electric fields in ultra-high vacuum. Quantum information is stored in hyperfine levels of the ions, with coherence times of seconds or longer. Ions are entangled via their shared collective vibrational modes (a “phonon bus”), giving natural all-to-all connectivity. Ions of the same isotope have identical internal level structure, avoiding the device-to-device parameter spread inherent to solid-state artificial qubits; actual gate performance nevertheless still depends on trap potentials, micromotion, motional heating, laser or microwave inhomogeneity and magnetic fields.
Recent progress. By 2016 teams at Oxford and NIST had pushed two-qubit gate fidelity to the 99.9% level[23]. Quantinuum uses a “quantum charge-coupled device” (QCCD) architecture, shuttling ions across on-chip electrodes to enable zoned operations and arbitrary connectivity[24]. Its 98-qubit Helios system, published in Nature in 2026, achieves average single-qubit gate error of 2.5×10⁻⁵ and two-qubit gate error of 7.9×10⁻⁴ across all operating zones, the best among published systems of comparable size[25]; in September 2026 a preprint on its Helix error-correction architecture (a [[20,2,6]] code) reported logical memory and logical gates that beat the physical baseline without postselection[26]. IonQ (which acquired Oxford Ionics) replaces laser control with microwave/RF signals generated by on-chip electrodes (“electronic qubit control”); on a two-ion prototype device it reported two-qubit gates without ground-state cooling with an estimated error of 8.4×10⁻⁵ (fidelity >99.99%)[27]. In September 2026 it launched the 256-qubit Superion platform, manufactured on semiconductor production lines, with delivery stated for 2027[28].
Bottlenecks. Gates are slow (typically tens to hundreds of microseconds, two to three orders of magnitude slower than superconducting gates); the number of ions in a single trap is limited, so scaling relies on ion shuttling or photonic interconnects, both of which add time and errors.
3.3 Neutral atoms: one of the fastest-scaling modalities
Principle. Tightly focused laser beams (“optical tweezers”) arrange individual neutral atoms (rubidium, caesium, ytterbium, strontium and others) into two-dimensional arrays. Atoms barely interact in their ground state and so have good coherence; to entangle them, lasers excite atoms to Rydberg states with very high principal quantum number, whose strong electric-dipole interaction produces a “Rydberg blockade” that enables controlled gates[29,30]. Crucially, the tweezers can move atoms during a computation, so connectivity is determined by software rather than by chip wiring.
Recent progress. In 2023 the Harvard team achieved 99.5% fidelity for parallel two-qubit gates on up to 60 atoms[31]. In 2025 the same group ran a system of more than 3,000 qubits coherently for over two hours with continuous atom reloading[32], and a Caltech team scaled a tweezer array to 6,100 highly coherent atomic qubits[33]. The 448-atom fault-tolerant architecture work described above places neutral atoms in the first tier of logical-level demonstrations[9]. On the industry side, Magne, the system Microsoft and Atom Computing are building for Denmark, is specified at more than 1,200 physical qubits and 50 logical qubits and is planned to become operational around the turn of 2026/27[34].
Bottlenecks. Gate operations, atom rearrangement, measurement and error-correction cycles are overall slower than on superconducting platforms, with full experimental or QEC cycles typically in the microsecond-to-millisecond range; the size of the gap depends strongly on which operations are compared, but for deep circuits wall-clock time is a real cost. Atom loss (leakage out of the computational space) requires dedicated detection and replenishment, and laser power, optical-control bandwidth and vacuum lifetime are engineering challenges at the scale of tens of thousands of qubits.
3.4 Photonic qubits: natural advantages in temperature and networking
Principle. Information is encoded either in a photon's polarisation, path or time bin (discrete variables, DV) or in continuous quadratures of the light field (continuous variables, CV). Photons barely interact with their environment, travel well at room temperature and are naturally suited to networking. The difficulty is that photons do not interact directly with each other: the 2001 KLM scheme showed that linear optics plus measurement suffices for universal computation, but the gates are probabilistic[35]. The two leading engineering approaches today are PsiQuantum's fusion-based quantum computation (FBQC), which builds fault-tolerant cluster states from small entangled states and “fusion measurements”[36], and Xanadu's CV approach based on the GKP encoding (which encodes a qubit in grid states of an oscillator)[37].
Recent progress. USTC's Jiuzhang series twice claimed quantum computational advantage in Gaussian boson sampling[38,39]. In 2025 PsiQuantum reported in Nature a silicon-photonics platform manufactured at GlobalFoundries: single-qubit state preparation and measurement fidelity of 99.98%, Hong–Ou–Mandel visibility of 99.50% between independent sources, two-qubit fusion fidelity of 99.22% and chip-to-chip interconnect fidelity of 99.72%, all conditioned on photon detection and excluding photon loss[40]. Xanadu's Aurora networks 35 photonic chips with 84 squeezers and 36 photon-number-resolving detectors; it synthesised a cluster state with 86.4 billion modes and demonstrated real-time decoding of a foliated distance-2 repetition code across 12 physical qubit modes. The authors describe it as a sub-performant scale model, in which squeezed states serve as placeholders for GKP states[41]; Xanadu's on-chip GKP state source was also published in Nature in 2025[42].
Bottlenecks. Photon loss is the main enemy: leading fault-tolerant photonic architectures require end-to-end loss well below what current systems achieve, with the precise loss threshold depending strongly on the encoding and architecture. Probabilistic sources require extensive multiplexing. Most optical and silicon-photonic components can operate at room temperature, but high-performance single-photon detectors (such as superconducting nanowire detectors) still require cryogenic cooling.
3.5 Silicon spin qubits: betting on the semiconductor industry
Principle. In 1998 Loss and DiVincenzo proposed using the spin of a single electron in a semiconductor quantum dot as a qubit[43]. Electron spins in silicon are weakly disturbed by their environment, and isotopically purified ²⁸Si removes nuclear-spin noise; qubits are only tens of nanometres across, comparable to transistors, so a million qubits could in principle be integrated on one chip using CMOS processes and production lines. Operating temperatures of about 0.1–1 K are higher than for superconducting qubits, making it easier to integrate cryogenic control electronics.
Recent progress. The first two-qubit logic gate in silicon appeared in 2015[44]; in 2022 QuTech and RIKEN simultaneously reported two-qubit gate fidelities above 99%, around the ~1% error threshold of common simplified surface-code noise models[45,46]. The key shift has been toward industrialisation: Intel has systematically probed single electrons across 300 mm wafers[47]; Diraq and imec showed that four randomly selected devices from a 300 mm foundry line all achieved single- and two-qubit gate fidelities above 99%, readout fidelity of up to 99.9% and T₁ of up to 9.5 s[48]. In 2026 HRL reported a digitally controlled silicon quantum processing unit[49], and imec/Diraq demonstrated coherent operation of an eight-qubit linear array[50]. Four of the 11 companies in Stage B of DARPA's QBI are on silicon-spin routes[51].
Bottlenecks. Demonstrations remain at the scale of a few to around ten qubits, far behind superconducting, ion and atom systems; parameter non-uniformity between quantum dots, crosstalk and wiring of two-dimensional arrays remain unsolved; error-correction demonstrations are at an early stage.
3.6 Colour centres (NV and others): workhorses of quantum networks and sensing
Principle. In the nitrogen-vacancy (NV) centre in diamond, a nitrogen atom replaces a carbon atom next to a lattice vacancy. Its electron spin can be initialised and read out with lasers and manipulated with microwaves at room temperature[52], and surrounding ¹³C nuclear spins can serve as long-lived memory qubits. More importantly, colour centres emit photons entangled with their spin states, making them natural “spin–photon interfaces” for linking remote quantum nodes. Silicon-vacancy (SiV) and tin-vacancy (SnV) centres and T centres in silicon are newer members of this family.
Recent progress. In 2015 the Delft team used NV electron spins 1.3 km apart to perform the first loophole-free Bell test[53], followed by a 10-qubit solid-state spin register[54], a three-node quantum network[55] and fault-tolerant operation of a logical qubit on a diamond processor[56]. A Harvard team used SiV centres to entangle two nodes over a 35 km telecom fibre network in Boston[57]. In 2026 QuTech used a microcavity to raise the effective photon-collection probability of an NV centre about tenfold (0.05% → 0.5%) and achieved coherent coupling of an SnV centre to a nanocavity[58].
Bottlenecks and positioning. Low photon-collection efficiency limits remote entanglement rates; deterministic fabrication of large numbers of uniform colour centres remains difficult; the number of controllable qubits per node is limited. The main arenas for colour centres are therefore interconnect nodes for quantum networks and distributed computing and quantum sensing (the latter already commercialised), rather than stand-alone large-scale computers.
3.7 Majorana topological qubits: high risk, high reward
Principle. Theory predicts that Majorana zero modes can appear at the ends of certain “topological superconductors”, such as semiconductor nanowires coated with a superconductor[59]. Intuitively, one fermionic degree of freedom is encoded non-locally in two spatially separated Majorana modes. Information is stored in the joint fermion parity of several zero modes and is therefore naturally robust against many local perturbations; exchanging (“braiding”) these non-Abelian quasiparticles can implement topologically protected logical operations[60,61]. Note that the Ising anyons associated with Majorana zero modes do not form a universal gate set through braiding alone; universal computation also requires non-topological operations such as measurement and magic-state injection/distillation[61]. Even so, if topological protection can be realised, the required error-correction overhead could be substantially reduced, which is why Microsoft has pursued this route for nearly two decades.
Recent progress and controversy. A 2018 Nature paper reporting “quantised Majorana conductance” was retracted in 2021[62], making the field especially cautious about similar claims. In February 2025 Microsoft published in Nature an interferometric single-shot parity measurement in InAs–Al hybrid devices[63] and simultaneously announced the Majorana 1 chip with “eight topological qubits”. However, the editorial peer-review note on the paper states explicitly that the results “do not represent evidence for the presence of Majorana zero modes” in the devices, and that the paper was published because its device architecture may be useful for future fusion experiments. In June 2026 Nature published a formal Matters Arising by Legg (University of St Andrews), arguing that the claimed parity readout occurred in a visibly disordered, likely gapless parameter regime and that the signal could arise from trivial mechanisms; in its reply Microsoft maintained its original interpretation[64]. As of this writing, the peer-reviewed literature has not confirmed the existence of topological qubits. A further distinction: Google and Quantinuum have “simulated” braiding of non-Abelian anyons on superconducting and ion processors[65,66]. This demonstrates the physical concepts but is not the same as realising topologically protected hardware qubits in a material.
Assessment. This is the technically riskiest of the seven modalities. If genuine topological protection is achieved, it could in theory substantially reduce the resource overhead of active quantum error correction; its eventual device density, gate speed and system-engineering advantages remain to be established experimentally. Until existence is independently confirmed, any qubit counts or timelines should be treated as corporate aspirations rather than engineering progress.
4 Side-by-side comparison
Table 1 summarises representative metrics for each modality from the public literature. Note that the figures come from different systems and measurement methods, and that “best single metric” and “large-system average” often differ by an order of magnitude. Figure 3 plots publicly reported two-qubit gate errors against experiment size to illustrate the tension between “high fidelity” and “large scale”, not to rank the modalities.
Table 1 Representative metrics and characteristics of the seven modalities (as of September 2026)
Modality | Representative public metrics | Scale | Main strengths | Main bottlenecks | Representative players |
|---|---|---|---|---|---|
Superconducting | Two-qubit gate error ~0.1–0.4%; gate time tens of ns; T₁ ~70–100 μs[6,20] | 100–150 qubits per chip; multi-chip modules | Fast gates (tens of ns); below-threshold QEC demonstrated; mature supply chain | Wiring and cryogenic heat load; TLS-defect drift; large qubit footprint | Google, IBM, USTC, AWS, Rigetti |
Trapped ion | Two-qubit gate error 7.9×10⁻⁴ (98-qubit system average)[25]; 8.4×10⁻⁵ on a two-ion prototype*[27] | ~100 qubits | Leading two-qubit fidelity; all-to-all connectivity; identical atomic level structure | Slow gates (10–100 μs or more); ion-shuttling and interconnect overhead | Quantinuum, IonQ |
Neutral atom | Parallel two-qubit gate fidelity 99.5%[31]; full cycles μs–ms | Thousands of atoms (up to 6,100)[33] | Largest qubit counts; reconfigurable connectivity; leading logical-qubit demonstrations | Slower operations; atom loss; complex laser and optical systems | QuEra, Atom Computing, Pasqal, Infleqtion |
Photonic | Fusion fidelity 99.22%, SPAM 99.98% (conditioned on photon detection)[40]; real-time decoding of a distance-2 repetition code in a sub-performant scale model (squeezed states as GKP placeholders)[41] | Very large cluster-state mode counts; no logical-qubit benchmark comparable to other platforms yet | Most optical/silicon-photonic components operate at room temperature; easy to network; silicon-photonics foundries | Photon loss; probabilistic sources; high-performance single-photon detectors still need cryogenics | PsiQuantum, Xanadu, Quandela, USTC |
Silicon spin | 300 mm foundry devices: single- and two-qubit gates >99%, T₁ up to 9.5 s[48] | ~10 qubits | Tiny qubits; CMOS-compatible; higher operating temperature | Uniformity and crosstalk; small scale; QEC at an early stage | Intel, Diraq, Quantum Motion, HRL, SQC |
Colour centre | Fault-tolerant operation of a logical qubit on a diamond processor[56]; room-temperature spin readout | ~10 qubits per node | Spin–photon interface; networking and sensing | Low photon-collection efficiency; uniform defect fabrication | QuTech, Harvard, Photonic Inc. |
Topological | Parity measurement demonstrated[63]; existence of zero modes not confirmed[64] | — | In theory, intrinsic noise robustness and reduced QEC overhead | Fundamental physics unverified; material disorder | Microsoft |
* Preprint, not yet peer reviewed. Metrics come from different systems and measurement protocols and are comparable only in order of magnitude.

Figure 3 Publicly reported two-qubit gate error versus experiment size (log–log; measurement protocols differ, so this is not a ranking). Marker shape distinguishes system averages, selected-pair prototypes, parallel gates and upper bounds. Data: Willow (CZ error distribution roughly 0.1–0.3%)[6]; Zuchongzhi 3.0[20]; Helios[25]; IonQ/Oxford Ionics two-ion prototype (* preprint)[27]; Harvard/MIT parallel gates[31]; Diraq/imec 300 mm devices, shown as an upper bound (error <1%)[48]. Photonic fusion fidelities are conditioned on photon detection and use a different basis, so they are not included.
5 Roadmaps and industry landscape
Table 2 lists the public roadmaps of the main players. All timelines are company statements and have historically often slipped; they should be read as intentions rather than commitments.
Table 2 Public roadmaps of the main players
Organisation | Modality | Recent milestones | Fault-tolerance target (company statements) |
|---|---|---|---|
IBM | Superconducting | Nighthawk 120 qubits and Loon test chip (Nov 2025); Kookaburra, first qLDPC module (planned 2026); Cockatoo, inter-module entanglement (2027) | Starling: 200 logical qubits, 100 million logical gates (2029)[21] |
Google Quantum AI | Superconducting + neutral atom | Willow below-threshold QEC (2024); Quantum Echoes (2025); neutral-atom programme added (Mar 2026) | Commercially relevant superconducting quantum computer by the end of the decade[22] |
Quantinuum | Trapped ion | Helios 98 qubits (Nature, 2026); Helix QEC architecture preprint (Sep 2026) | Sol: expected 2027, up to ~100 logical qubits; Apollo: expected 2029, hundreds of logical qubits and universal fault tolerance[67] |
IonQ | Trapped ion (electronic control) | >99.99% two-qubit gates on a two-ion prototype (2025, preprint)[27]; Superion 256 launched (Sep 2026; delivery stated for 2027)[28] | Millions of physical qubits by 2030[68] |
Microsoft + Atom Computing | Neutral atom | 24 entangled logical qubits (2024, preprint)[16] | Magne: >1,200 physical / 50 logical qubits, planned operation around the turn of 2026/27[34] |
QuEra (with Harvard/MIT) | Neutral atom | 448-atom fault-tolerant architecture (2025, with Harvard/MIT)[9] | Scaling of logical qubits (no unified public timeline) |
PsiQuantum | Photonic (FBQC) | Silicon-photonics manufacturing platform (Nature, 2025)[40]; US$1 billion Series E to build facilities in Brisbane and Chicago (Sep 2025)[69] | Million-qubit-scale, utility-scale fault-tolerant machine (no specific year announced) |
Xanadu | Photonic (GKP) | Aurora modular networked system (Nature, 2025)[41]; Qubit Factory under construction (2026–2027) | Fault tolerance in 2028–2029; up to 200 logical qubits in 2029; over 1,000 logical qubits in 2031[70] |
Microsoft | Topological | Majorana 1 chip (2025, disputed) | Fault-tolerant machine built on topological qubits (timeline not independently verified) |
Timelines are company statements and have historically often slipped; for reference only.
Capital. According to McKinsey's Quantum Technology Monitor 2026, quantum-technology start-ups raised US$12.6 billion in 2025, about 6.3 times the 2024 amount, with roughly 90% going to quantum computing; quantum-computing companies' revenues exceeded US$1 billion for the first time that year[71]. Public markets were similarly active: Quantinuum began trading on Nasdaq on 4 June 2026, raising US$1.68 billion[72]; Xanadu listed on Nasdaq and the Toronto Stock Exchange in March 2026 through a SPAC merger[73]; IonQ made a string of acquisitions in 2025, including Oxford Ionics. Capital is highly concentrated in the leading firms, with the ten largest deals accounting for about 60% of the total[71].
Policy. DARPA's Quantum Benchmarking Initiative (QBI) aims to assess whether a utility-scale quantum computer, one whose computational value exceeds its cost, can be built by 2033. The 11 companies that entered Stage B in November 2025 span five hardware modalities: superconducting (IBM, Nord Quantique), trapped ion (IonQ, Quantinuum), neutral atom (Atom Computing, QuEra), silicon spin (Diraq, Photonic, Quantum Motion, Silicon Quantum Computing) and photonic (Xanadu)[51]. This distribution itself shows that even the most specialised evaluator has not yet bet on a single modality.
Three observations from an economic perspective. First, the sources of economies of scale differ by modality: superconducting and silicon-spin qubits rely on semiconductor-style learning curves and yield improvements, atoms and ions on falling costs of lasers and optical systems, and photonics on mature silicon-photonics production lines. Their marginal-cost curves therefore have different shapes, and the end state need not be winner-takes-all. Second, the cost of logical quantum computation is not determined by the number of physical qubits alone, but jointly by the physical error rate, the efficiency of the error-correcting code, the target logical error rate, gate speed, connectivity and the control systems. Below the error-correction threshold, further lowering the physical error rate can reduce the code distance needed to reach a given logical error rate and thus substantially reduce physical-qubit and runtime overhead; but this relationship depends heavily on the specific code and noise model, and there is no cross-platform conversion ratio. A more meaningful basis for comparison is therefore the cost per reliable logical operation, rather than the price of a physical or logical qubit. Third, until useful fault-tolerant machines arrive, industry revenues come mainly from government and research procurement, cloud access and consulting; valuations depend heavily on expectations about technology timelines, implying significant volatility risk.
6 Implications for cryptography and blockchains
Shor's algorithm can factor large integers and solve discrete logarithms in polynomial time, thereby breaking RSA and elliptic-curve cryptography (ECC). The key question is how large a quantum computer is needed. Figure 4 shows that resource estimates have fallen sharply over the past seven years: the physical qubits needed to break RSA-2048 dropped from about 20 million (2019) to under 1 million (2025, with a runtime of about a week)[74,75]. A resource estimate by the Google Quantum AI team with cryptographers, first released in March 2026 and published in PRX Quantum in August 2026, shows that 256-bit elliptic-curve discrete logarithms (the basis of Bitcoin and Ethereum signatures) can be solved with <1,200 logical qubits and <90 million Toffoli gates, or <1,450 logical qubits and <70 million Toffoli gates. Assuming a physical error rate of 10⁻³ and a superconducting architecture with planar connectivity, this corresponds to fewer than about 500,000 physical qubits and a runtime of minutes, below the requirement for RSA-2048[76].

Figure 4 Resource estimates for the physical qubits needed to break public-key cryptography, compared with realised system sizes. Estimates assume superconducting-type hardware, about 0.1% physical error and surface-code error correction; preprints based on other architectures (e.g. high-rate qLDPC codes or neutral atoms) give lower numbers under more aggressive assumptions. Realised physical-qubit counts are not equivalent to the fault-tolerant qubits these estimates assume.
This trend should be read in a balanced way. On the one hand, a large engineering gap remains between current hardware and these fault-tolerant resources: today's systems have demonstrated at most around a hundred low-distance logical qubits, whereas the estimates require roughly a thousand high-quality logical qubits, tens of millions of non-Clifford logical operations, and continuous error-corrected operation for minutes to about a week. On the other hand, falling resource estimates increase the need to plan post-quantum migration early, and the threat models differ. For data that must remain confidential for many years, “harvest now, decrypt later” means that encryption must be migrated before cryptographically relevant quantum computers mature. For blockchains, the risk instead comes from the future recovery of private keys from public keys that are already exposed on-chain, enabling signature forgery, and from large amounts of dormant assets that cannot migrate on their own. NIST published its first post-quantum cryptography standards (ML-KEM, ML-DSA, SLH-DSA) in August 2024[77]. For blockchains, migrating signature schemes involves consensus upgrades and decisions about dormant assets, and these governance and mechanism-design questions may prove harder than the cryptography itself.
7 Conclusions and watch list for 2026–2027
Quantum computing has crossed the threshold of demonstrating below-threshold quantum error correction experimentally on several platforms, and the competition is shifting to whether this can be scaled at acceptable resource cost. Different modalities make different trade-offs among speed, fidelity, scale and manufacturability. In the near term a division of labour by application seems more likely than a single winner: for example, superconducting qubits and trapped ions for deep-circuit computation, neutral atoms for large logical-qubit arrays, and photons and colour centres for interconnects and networks. Signals worth watching over the next 12–18 months include:
- Logical gates, not just logical memory: public data showing logical-gate error rates ≤10⁻⁴ over hundreds of consecutive error-correction rounds without postselection.
- Delivery of IBM Kookaburra and Microsoft/Atom Magne: tests, respectively, of the feasibility of qLDPC codes on superconducting hardware and of the engineering maturity of neutral-atom logical systems.
- Independent verification of Majorana modes: the expanded data sets Microsoft has committed to release, and third-party replications.
- Photon loss and silicon-spin arrays: whether end-to-end loss in photonic devices approaches fault-tolerance requirements, and whether silicon spin moves from one-dimensional eight-qubit arrays to two-dimensional arrays of tens of qubits with error correction.
- Further falls in resource estimates and progress on post-quantum migration: especially governance arrangements in blockchain ecosystems for upgrading signature schemes.
Data and methods
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References
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Cite this report
Liu, Y. (2026). Quantum Computing Modalities: Principles, Recent Progress and Industry Landscape. Quantum Economics AI Lab Research Note, September 2026. https://www.quantecon.ai/applied-research/quantum-computing-landscape
BibTeX
@techreport{liu2026quantumcomputinglandscape,
author = {Liu, Yulin},
title = {Quantum Computing Modalities: Principles, Recent Progress and Industry Landscape},
institution = {Quantum Economics AI Lab},
type = {Research Note},
year = {2026},
url = {https://www.quantecon.ai/applied-research/quantum-computing-landscape}
}